This invention relates to power switching transistors, and more specifically to an Insulated Gate Transistor with increasing latching current capacity.
Field effect and bipolar transistors have different characteristics, suiting them for different uses.
In bipolar transistors, bipolar ("majority" and "minority" carrier) conduction through PN junctions and a large base area permits a high current density. However, PN junctions have a capacitance that must be charged in turning the transistor on, and discharged in turning it off, which slows the switching speed of bipolar transistors. In addition, excess minority and majority carriers in the case when the transistor begins to turn off must recombine before the transistor is completely turned off. During the relatively long intervals for switching on or off, the voltage and current through the transistor change, in opposite directions, and at intermediate values their product, power, is higher than when the transistor is not switching. The transistor dissipates power as heat. The ability of silicon to dissipate heat limits the current density rating of bipolar transistors placed in a given area of semiconductor material.
A metal oxide semiconductor field effect transistor (MOSFET) switches faster and dissipates less heat than a bipolar transistor of the same rating. A MOSFET is operated by applying a voltage potential to its gate electrode to establish an electric field from the gate through a layer of gate oxide and into underlying semiconductor material. The field inverts charges in an adjacent channel region beneath the oxide in the semiconductor material, which enables a current of majority charge carriers to flow between appropriately biased source and drain regions connected by the channel region. Having no counter-current of minority charge carriers in need of recombining with majority charge carriers, MOSFETs switch on and off very rapidly. Yet, with the channel being the only conduction path, a MOSFET does not conduct as much current as a same-size bipolar transistor rated for the same voltage. Consequently, MOSFETs have a lower current density.
An ideal power switching device would switch on and off at high speed in MOSFET mode, to conduct current at high density in bipolar mode when on, and be controllable by a gate electrode. Vertical MOS and double diffused MOS (DMOS) transistors are MOSFET structures adapted for power switching, i.e. switching large currents on and off.
Referring to FIG. 1a (not drawn to scale), in a typical prior art DMOS transistor 10, an N-type semiconductor substrate with upper surface 12 provides a drain region 18. Drain 18 includes upper drain region 18ub and lower drain region 181. Backside terminal 15 contacts drain 18. Gate oxide layer 20 on surface 12 supports and insulates polysilicon gate 22b above upper drain 18ub. Referring to the portion of FIG. 1a near gate oxide 20 and terminal 32a, shown in the enlarged view of FIG. 1b, on either side of upper drain 18ub a P-type semiconductor channel body well such as well 24a has a thin wall 25b for forming conduction channel 26b beneath upper surface 12. P type well 24a contains source region 28b, which is heavily doped with N-type impurities. In a power DMOS structure, the edge regions of a well such as well 24a preferably each contain separate source regions 28a and 28b, (for clarity not shown in FIG. 1b but shown in FIG. 2a which relates to a slightly different structure). As shown in FIG. 2a, each source region 28a,b,c,d is adjacent one of gates 22a, 22b, and 22c. Each gate 22a, 22b, 22c bridges a respective upper drain region 18ua, 18ub, 18uc separating two adjacent well regions 24. Structure 10 is bilaterally symmetrical about an imaginary vertical center plane along center line C.sub.L (FIG. 1a) through the center of gate 22b and perpendicular to the plane of the drawing.
Referring to FIG. 1b, with a gate voltage applied to gate 22b which is greater than the conduction threshold voltage for channel 26b, and with drain 18 biased positively an appropriate amount with respect to source 28b, electrons flow from source 28b through channel 26b to upper drain 18ub, as indicated by the e.sup.- arrow, and flow out drain terminal 15 (FIG. 1a). If source-well junction 27b becomes forward biased by more than 0.7 volts, thin and lightly doped well wall 25b functions as a base of a parasitic bipolar transistor. Electrons flow from source 28b not only through channel 26b but across forward biased junction 27b and through other parts of well 24a, and across junction 34a into lower drain 181. In this event, the source-channel-drain structure works as a parasitic emitter-base-collector bipolar transistor. Bipolar conduction continues uncontrolled, even after gate lead 30b is externally shorted to emitter lead 32a to eliminate the field forming channel 26b and stop FET conduction. To stop bipolar conduction, the source-to-drain voltage difference must be externally reduced until junction 27b is no longer forward biased by as much as 0.7 volts.
To counter forward biasing of junction 27b, source region 28b and well 24a are typically shorted together by a source-emitter aluminum contact terminal 32a positioned on wafer surface 12 at point "S" (FIG. 1b) where source-well junction 27b meets surface 12, remote from channel 26b since shorting junction 27b adjacent channel 26b would interfere with current through the channel. Still, at a sufficient source-drain bias voltage (30 to 1000 votls, depending on the design, and hence rating, of device 10), reverse biased well-drain junction 34a breaks down, and a hole current starts from drain 18 across junction 34a and through well 24a. If, in spite of source-emitter shorting terminal 32a, sufficient current flows as illustrated by holes along a critical path 50 extending from upper drain 18ub laterally through the "pinched" region 23 of well 24a, parallel to junction 27b to terminal 32a, and if path 50 is sufficiently resistive, the voltage difference set up along path 50 will forward bias junction 27b around point "F" near upper drain 18ub (FIG. 1b), starting parasitic bipolar mode conduction and circumventing gate 22b turn-off ability.
Despite an externally applied reverse bias sufficient to break down junction 34a, forward biasing of junction 27b can be deterred if the voltage drop along path 50 is reduced, by narrowing source region 28b to shorten path 50, or by decreasing a resistivity of semiconductor material in the path.
U.S. Pat. No. 4,345,265 to Blanchard reduces the current and voltage difference along a path 50 in a DMOS transistor by selectively enlarging and increasing the conductivity of well 24 remote from channel 26 to form a "deep well" 66 (not shown for a DMOS transistor but shown in FIG. 2a for an IGT) to divert hole current from path 50. The P type conductivity of well 24a cannot be increased in well wall 25b near upper drain 18ub because that would prevent the field applied by gate 22b from inverting the conductivity of that region to form a conducting channel 26b. The deep well 66a portion of well 24a provides a more constant breakdown voltage along junction 34a. Also, the conductivity of well 24a being increased in the portion of deep well 66a near contact 32a provides a lower resistance path or short between the interior of well 24a and source region 28b. For voltage ratings exceeding 100 volts, the increased current density of DMOS transistors with deep wells 66 is still not comparable to that of bipolar transistors, and, for similar voltage ratings and die areas, DMOS transistors generally have a higher "on" resistance than bipolar transistors.
An insulated gate transistor (IGT) is a dual mode DMOS-like structure which switches on at high speed in MOS mode and obtains controlled high density conduction in bipolar mode. FIG. 2a (not to scale) shows a prior art IGT device. The regions in each space in FIG. 2a between the vertical axes of a gate terminal 30 on one side and a source-collector terminal 32 on the other side form respective IGTs 60a, 60b, 60c, and 60d. FIG. 2b shows the equivalent circuit for an IGT superimposed over the regions forming an IGT 60, with junctions 27, 34, and 67 indicated by dashed lines.
To operate both as a field effect transistor and as a bipolar transistor, an IGT such as 60b comprises four layers, in which three layers or regions 28b, 24a, and 18 of N+, P-, and N- type semiconductor material, respectively, are used for a source, channel body, and drain in an N-channel FET structure as in a DMOS transistor. For simplicity, corresponding regions of the structures of FIGS. 1a and 2a are numbered the same. Three lower regions 24a, 18, and 62 of P+, N-, and P+ type material, respectively, are used for a collector, base, and emitter in a bipolar transistor structure QL. The added fourth layer P+ emitter region (FIG. 2a) is provided by substrate 62, on which regions 18 are epitaxially grown. When starting to turn on, IGT 60b operates only in FET mode. While turning on, forward biased junction 67 makes region 62 function as part of drain 181. When IGT 60b completes turning on, however, regions of IGT 60b also function in bipolar mode. Thus region 18 functions not only as a drain of an FET but also as the base of bipolar transistor QL, and well 24a functions not only as a channel of an FET but also as the collector 24 of transistor QL (FIG. 2b). Conventionally, P-implanted wells 24a and 24b (FIG. 2a) contain, in regions closely adjacent to but separated from upper drain region 18ub, N-implanted source regions 28b and 28c, respectively. The laterally opposed sides of each well 24a and 24b contain, as shown in FIG. 2a, source regions 28a, 28b, 28c and 28d. Channels 26a, 26b, 26c, and 26d are respectively formed between source regions 28a, 28b, 28c and 28d on the one hand, and the directly adjacent upper drain regions 18ua, 18ub, and 18uc, on the other hand.
Referring to both FIGS. 2a and 2b, a negative potential applied to terminal 68, relative to the potential of terminal 32a, reverse-biases junction 67, and blocks reverse current, for example during inductive load switching. A positive potential at terminal 68 relative the potential at terminal 32a reverse biases junction 34a and blocks forward current. At less than the breakdown voltage of either junction 34a or 67, lack of current through region 18, the base of transistor QL (FIG. 2b), prevents bipolar mode conduction in either direction.
Referring now to IGT 60b in FIG. 2a, when a positive voltage is applied to gate 22b, and drain region 18 is biased positive relative to source region 28b, electrons flow through channel 26b. This FET mode electron conduction provides a base current for bipolar transistor QL. FET mode electron current through forward biased junction 67 towards emitter 62 causes an opposite current of holes to be injected from emitter 62 back across junction 67. Minority carrier holes in base region 18 combine with electrons or are swept across reverse biased junction 34a to collector 24a of transistor QL. Bipolar conduction in an IGT increases (improves) current density over a DMOSFET, by as much as a factor of 19 (IEEE Trans. on Electron Devices, Vol. ED-31, No. 6, June 84, pg. 821).
Bipolar mode conduction is intended in the three regions 62, 18, and 24a, respectively, which form PNP transistor QL in the lower three regions of IGT 60b. However, regions 62, 18 and 24a, plus fourth region 28b unfortunately constitute a thyristor. If the collector current of transistor QL along path 50 sufficiently forward biases portions of junction 27b removed from terminal 32a, the three regions 18, 24a, and 28b operate as a parasitic bipolar NPN transistor QP (FIG. 2b). With transistors QL and QP both conducting, the four layer thyristor structure 60b "latches" into a self-perpetuating state of bipolar conduction, which cannot be turned off by removing the voltage bias on gate 22b to stop FET mode conduction. Thus control through gate 22b over the bipolar current is lost. Regions of IGTs 60a, 60c, and 60d function identically to correspondingly numbered but differently lettered regions of IGT 60b.
To switch power between terminals 68 and 32a at increased voltage differences, in prior art IGT designs the voltage drop along critical path 50 has been limited, as in DMOS transistors, by reducing the width of source well 28b, and hence reducing the length of critical path 50. U.S. Pat. No. 4,443,931 to Baliga increases the size and conductivity of collector wells 24 in deep wells 66a and 66b remote from critical paths 50, to divert current and thus reduce the voltage drop along critical path 50 in an IGT and thereby reduce the forward voltage bias from well 24a to region 28b across junction 27b. The prior art patents cited above are hereby incorporated by reference and may be consulted for further details with respect to conventional IGTs, their manufacture and/or use.
An enlarged and more conductive well 66a diverts some current from critical path 50 and increases the latching current density of IGT 60b. However, collector wells of increased size and conductivity are of limited effectiveness in diverting current from critical path 50. Hole current tends to flow only within a diffusion length of the electron current path (which is through channel 26b), so not enough hole current is diverted through deep well 66a. Controllable current density ratings of conventional IGTs are still limited by latching caused by current along critical path 50. It is therefore desirable to further increase the latching current density of IGTs to expand their range of reliable and useful operation.